| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| U_feuxcarrefour|Sreg0_s76 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_s73 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_s69 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_s67 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_s66 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_s56 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_s45 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_s42 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_s39 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_s38 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_s32 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_s29 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_s28 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_s15 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_s0 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_machine_tempo_9 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_machine_tempo_8 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_machine_tempo_7 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_machine_tempo_6 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_machine_tempo_5 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_machine_tempo_4 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_machine_tempo_31 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_machine_tempo_30 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_machine_tempo_3 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_machine_tempo_29 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_machine_tempo_28 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_machine_tempo_27 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_machine_tempo_26 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_machine_tempo_25 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_machine_tempo_24 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_machine_tempo_23 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_machine_tempo_22 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_machine_tempo_21 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_machine_tempo_20 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_machine_tempo_2 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_machine_tempo_19 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_machine_tempo_18 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_machine_tempo_17 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_machine_tempo_16 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_machine_tempo_15 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_machine_tempo_14 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_machine_tempo_13 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_machine_tempo_12 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_machine_tempo_11 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_machine_tempo_10 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_machine_tempo_1 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_machine_tempo_0 |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|Sreg0_init |
4 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|LPM_COMPARE_32_32_8|auto_generated |
64 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|LPM_COMPARE_32_32_7|auto_generated |
64 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|LPM_COMPARE_32_32_6|auto_generated |
64 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|LPM_COMPARE_32_32_5|auto_generated |
64 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|LPM_COMPARE_32_32_4|auto_generated |
64 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|LPM_COMPARE_32_32_3|auto_generated |
64 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|LPM_COMPARE_32_32_2|auto_generated |
64 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|LPM_COMPARE_32_32_1|auto_generated |
64 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|i1451|lpm_add_sub_inst|auto_generated |
63 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour|i1451 |
63 |
31 |
0 |
31 |
31 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
| U_feuxcarrefour |
4 |
0 |
1 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|divisor_2_0_component_c11 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|divisor_main_component_c10 |
35 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|divisor_25_0_component_c9|U2 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|divisor_25_0_component_c9|U1 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|divisor_25_0_component_c9 |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|divisor_9_0_component_c8|U2 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|divisor_9_0_component_c8|U1 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|divisor_9_0_component_c8 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|divisor_1_5_component_c7 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|divisor_2_5_component_c6 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|divisor_3_0_component_c5 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|divisor_5_0_component_c4 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|divisor_3_0_component_c3 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|divisor_5_0_component_c2 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|divisor_3_0_component_c1 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|divisor_5_0_component_c0 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|user2_register |
8 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|user1_register |
8 |
0 |
0 |
0 |
33 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|control_register |
8 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|tap1|id_reg_unit |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ|tap1 |
5 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3|U_FREQ |
5 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U3 |
5 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| U1_U2|altsyncram_component|auto_generated |
20 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1_U2 |
20 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1_U1|U1|U_LA16PORT|U_BUFFREG |
14 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1_U1|U1|U_LA16PORT|U_TAP|id_reg_unit |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1_U1|U1|U_LA16PORT|U_TAP |
7 |
0 |
0 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1_U1|U1|U_LA16PORT|U_NX_MODULE|U_SELREG |
9 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1_U1|U1|U_LA16PORT|U_NX_MODULE|U_MAGNITREG |
9 |
0 |
0 |
0 |
15 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1_U1|U1|U_LA16PORT|U_NX_MODULE|U_ECNTREG |
9 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1_U1|U1|U_LA16PORT|U_NX_MODULE|U_CURSORREG |
9 |
0 |
0 |
0 |
22 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1_U1|U1|U_LA16PORT|U_NX_MODULE|U_TRMASKREG |
8 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1_U1|U1|U_LA16PORT|U_NX_MODULE|U_TRWORD2REG |
9 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1_U1|U1|U_LA16PORT|U_NX_MODULE|U_TRWORDREG |
8 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1_U1|U1|U_LA16PORT|U_NX_MODULE|U_CTRLREG |
10 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1_U1|U1|U_LA16PORT|U_NX_MODULE|U_CFGREG |
9 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1_U1|U1|U_LA16PORT|U_NX_MODULE|U_NEXUS_CTRL_FSM |
5 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1_U1|U1|U_LA16PORT|U_NX_MODULE |
26 |
0 |
0 |
0 |
96 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1_U1|U1|U_LA16PORT |
33 |
0 |
0 |
0 |
104 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1_U1|U1|U_FSM |
128 |
0 |
0 |
0 |
102 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1_U1|U1|U_DUMP |
59 |
0 |
0 |
0 |
52 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1_U1|U1 |
100 |
0 |
0 |
0 |
172 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| U1_U1 |
31 |
6 |
0 |
6 |
20 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |