Hierarchy Input Constant Input Unused Input Floating Input Output Constant Output Unused Output Floating Output Bidir Constant Bidir Unused Bidir Input only Bidir Output only Bidir
U_Open_bus_TP3_xram|Timer_4 4 2 0 2 1 2 2 2 0 0 0 0 0
U_Open_bus_TP3_xram|Timer_3 4 2 0 2 1 2 2 2 0 0 0 0 0
U_Open_bus_TP3_xram|Timer_2 4 2 0 2 1 2 2 2 0 0 0 0 0
U_Open_bus_TP3_xram|Timer_1 4 2 0 2 1 2 2 2 0 0 0 0 0
U_Open_bus_TP3_xram|Timer_0 4 2 0 2 1 2 2 2 0 0 0 0 0
U_Open_bus_TP3_xram|State_state_write_setup 4 2 0 2 1 2 2 2 0 0 0 0 0
U_Open_bus_TP3_xram|State_state_write_pulse 4 2 0 2 1 2 2 2 0 0 0 0 0
U_Open_bus_TP3_xram|State_state_write_hold 4 2 0 2 1 2 2 2 0 0 0 0 0
U_Open_bus_TP3_xram|State_state_write_ack 4 2 0 2 1 2 2 2 0 0 0 0 0
U_Open_bus_TP3_xram|State_state_read_ack 4 2 0 2 1 2 2 2 0 0 0 0 0
U_Open_bus_TP3_xram|State_state_addresssetup 4 2 0 2 1 2 2 2 0 0 0 0 0
U_Open_bus_TP3_xram|i512|lpm_add_sub_inst|auto_generated 9 0 0 0 5 0 0 0 0 0 0 0 0
U_Open_bus_TP3_xram|i512 9 4 0 4 4 4 4 4 0 0 0 0 0
U_Open_bus_TP3_xram 61 0 2 0 79 0 0 0 32 0 0 0 0
U_Open_bus_TP3_WB_MULTIMASTER_1|State_1 4 2 0 2 1 2 2 2 0 0 0 0 0
U_Open_bus_TP3_WB_MULTIMASTER_1|State_0 4 2 0 2 1 2 2 2 0 0 0 0 0
U_Open_bus_TP3_WB_MULTIMASTER_1 153 0 0 0 125 0 0 0 0 0 0 0 0
U_Open_bus_TP3_WB_INTERCON_2|UseBadDecode 4 2 0 2 1 2 2 2 0 0 0 0 0
U_Open_bus_TP3_WB_INTERCON_2|LPM_COMPARE_8_8_2|auto_generated 16 0 0 0 1 0 0 0 0 0 0 0 0
U_Open_bus_TP3_WB_INTERCON_2|DecodeAddr_7 5 2 0 2 1 2 2 2 0 0 0 0 0
U_Open_bus_TP3_WB_INTERCON_2|DecodeAddr_6 5 2 0 2 1 2 2 2 0 0 0 0 0
U_Open_bus_TP3_WB_INTERCON_2|DecodeAddr_5 5 2 0 2 1 2 2 2 0 0 0 0 0
U_Open_bus_TP3_WB_INTERCON_2|DecodeAddr_4 5 2 0 2 1 2 2 2 0 0 0 0 0
U_Open_bus_TP3_WB_INTERCON_2|DecodeAddr_3 5 2 0 2 1 2 2 2 0 0 0 0 0
U_Open_bus_TP3_WB_INTERCON_2|DecodeAddr_2 5 2 0 2 1 2 2 2 0 0 0 0 0
U_Open_bus_TP3_WB_INTERCON_2|DecodeAddr_1 5 2 0 2 1 2 2 2 0 0 0 0 0
U_Open_bus_TP3_WB_INTERCON_2|DecodeAddr_0 5 2 0 2 1 2 2 2 0 0 0 0 0
U_Open_bus_TP3_WB_INTERCON_2|Bad_Decode 4 2 0 2 1 2 2 2 0 0 0 0 0
U_Open_bus_TP3_WB_INTERCON_2 105 0 4 0 92 0 0 0 0 0 0 0 0
U_Open_bus_TP3_WB_INTERCON_1|UseBadDecode 4 2 0 2 1 2 2 2 0 0 0 0 0
U_Open_bus_TP3_WB_INTERCON_1|LPM_COMPARE_8_8_1|auto_generated 16 0 0 0 1 0 0 0 0 0 0 0 0
U_Open_bus_TP3_WB_INTERCON_1|DecodeAddr_7 5 2 0 2 1 2 2 2 0 0 0 0 0
U_Open_bus_TP3_WB_INTERCON_1|DecodeAddr_6 5 2 0 2 1 2 2 2 0 0 0 0 0
U_Open_bus_TP3_WB_INTERCON_1|DecodeAddr_5 5 2 0 2 1 2 2 2 0 0 0 0 0
U_Open_bus_TP3_WB_INTERCON_1|DecodeAddr_4 5 2 0 2 1 2 2 2 0 0 0 0 0
U_Open_bus_TP3_WB_INTERCON_1|DecodeAddr_3 5 2 0 2 1 2 2 2 0 0 0 0 0
U_Open_bus_TP3_WB_INTERCON_1|DecodeAddr_2 5 2 0 2 1 2 2 2 0 0 0 0 0
U_Open_bus_TP3_WB_INTERCON_1|DecodeAddr_1 5 2 0 2 1 2 2 2 0 0 0 0 0
U_Open_bus_TP3_WB_INTERCON_1|DecodeAddr_0 5 2 0 2 1 2 2 2 0 0 0 0 0
U_Open_bus_TP3_WB_INTERCON_1|Bad_Decode 4 2 0 2 1 2 2 2 0 0 0 0 0
U_Open_bus_TP3_WB_INTERCON_1 115 0 10 0 102 0 0 0 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|output_reg_31 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|output_reg_30 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|output_reg_29 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|output_reg_28 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|output_reg_27 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|output_reg_26 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|output_reg_25 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|output_reg_24 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|output_reg_23 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|output_reg_22 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|output_reg_21 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|output_reg_20 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|output_reg_19 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|output_reg_18 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|output_reg_17 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|output_reg_16 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|n5r 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_WE_O 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_SEL_O_3 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_SEL_O_2 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_SEL_O_1 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_SEL_O_0 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_DAT_O_9 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_DAT_O_8 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_DAT_O_7 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_DAT_O_6 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_DAT_O_5 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_DAT_O_4 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_DAT_O_31 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_DAT_O_30 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_DAT_O_3 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_DAT_O_29 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_DAT_O_28 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_DAT_O_27 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_DAT_O_26 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_DAT_O_25 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_DAT_O_24 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_DAT_O_23 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_DAT_O_22 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_DAT_O_21 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_DAT_O_20 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_DAT_O_2 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_DAT_O_19 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_DAT_O_18 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_DAT_O_17 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_DAT_O_16 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_DAT_O_15 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_DAT_O_14 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_DAT_O_13 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_DAT_O_12 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_DAT_O_11 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_DAT_O_10 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_DAT_O_1 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_DAT_O_0 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_ADR_O_9 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_ADR_O_8 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_ADR_O_7 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_ADR_O_6 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_ADR_O_5 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_ADR_O_4 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_ADR_O_31 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_ADR_O_30 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_ADR_O_3 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_ADR_O_29 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_ADR_O_28 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_ADR_O_27 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_ADR_O_26 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_ADR_O_25 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_ADR_O_24 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_ADR_O_23 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_ADR_O_22 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_ADR_O_21 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_ADR_O_20 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_ADR_O_2 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_ADR_O_19 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_ADR_O_18 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_ADR_O_17 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_ADR_O_16 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_ADR_O_15 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_ADR_O_14 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_ADR_O_13 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_ADR_O_12 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_ADR_O_11 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_ADR_O_10 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_ADR_O_1 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|INST_me_ADR_O_0 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_9 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_8 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_7 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_63 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_62 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_61 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_60 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_6 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_59 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_58 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_57 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_56 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_55 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_54 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_53 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_52 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_51 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_50 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_5 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_49 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_48 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_47 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_46 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_45 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_44 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_43 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_42 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_41 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_40 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_4 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_39 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_38 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_37 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_36 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_35 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_34 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_33 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_32 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_31 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_30 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_3 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_29 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_28 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_27 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_26 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_25 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_24 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_23 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_22 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_21 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_20 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_2 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_19 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_18 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_17 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_16 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_15 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_14 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_13 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_12 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_11 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_10 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_1 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|input_reg_0 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|xori_0_in_9 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|xori_0_in_15 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|xori_0_in_14 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|xori_0_in_13 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|xori_0_in_12 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|xori_0_in_11 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|xori_0_in_10 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|xor_0_retval_7 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|xor_0_retval_6 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|xor_0_retval_5 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|xor_0_retval_4 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|xor_0_retval_3 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|xor_0_retval_2 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|xor_0_retval_1 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|xor_0_retval_0 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|vld_me_8_0_address_9 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|vld_me_8_0_address_8 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|vld_me_8_0_address_7 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|vld_me_8_0_address_6 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|vld_me_8_0_address_5 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|vld_me_8_0_address_4 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|vld_me_8_0_address_31 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|vld_me_8_0_address_30 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|vld_me_8_0_address_3 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|vld_me_8_0_address_29 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|vld_me_8_0_address_28 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|vld_me_8_0_address_27 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|vld_me_8_0_address_26 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|vld_me_8_0_address_25 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|vld_me_8_0_address_24 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|vld_me_8_0_address_23 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|vld_me_8_0_address_22 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|vld_me_8_0_address_21 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|vld_me_8_0_address_20 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|vld_me_8_0_address_2 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|vld_me_8_0_address_19 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|vld_me_8_0_address_18 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|vld_me_8_0_address_17 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|vld_me_8_0_address_16 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|vld_me_8_0_address_15 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|vld_me_8_0_address_14 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|vld_me_8_0_address_13 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|vld_me_8_0_address_12 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|vld_me_8_0_address_11 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|vld_me_8_0_address_10 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|vld_me_8_0_address_1 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|vld_me_8_0_address_0 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|vld_me_8_0|latched_mau_low_1 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|vld_me_8_0|latched_mau_low_0 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|vld_me_8_0 68 33 0 33 77 33 33 33 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|subui_v2_0_in_9 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|subui_v2_0_in_8 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|subui_v2_0_in_7 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|subui_v2_0_in_6 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|subui_v2_0_in_5 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|subui_v2_0_in_4 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|subui_v2_0_in_31 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|subui_v2_0_in_30 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|subui_v2_0_in_3 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|subui_v2_0_in_29 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|subui_v2_0_in_28 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|subui_v2_0_in_27 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|subui_v2_0_in_26 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|subui_v2_0_in_25 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|subui_v2_0_in_24 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|subui_v2_0_in_23 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|subui_v2_0_in_22 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|subui_v2_0_in_21 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|subui_v2_0_in_20 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|subui_v2_0_in_2 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|subui_v2_0_in_19 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|subui_v2_0_in_18 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|subui_v2_0_in_17 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|subui_v2_0_in_16 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|subui_v2_0_in_15 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|subui_v2_0_in_14 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|subui_v2_0_in_13 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|subui_v2_0_in_12 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|subui_v2_0_in_11 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|subui_v2_0_in_10 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|subui_v2_0_in_1 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|subui_v2_0_in_0 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|subui_0_in_3 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|subui_0_in_2 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|subui_0_in_1 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|subui_0_in_0 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|vld_me_8_0_start 4 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|mux_0_retval_0 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|i1525|lpm_add_sub_inst|auto_generated 7 0 0 0 4 0 0 0 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|i1525 7 3 0 3 3 3 3 3 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|i1524|lpm_add_sub_inst|auto_generated 63 0 0 0 32 0 0 0 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|i1524 63 31 0 31 31 31 31 31 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|i1523|lpm_add_sub_inst|auto_generated 63 0 0 0 32 0 0 0 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|i1523 63 31 0 31 31 31 31 31 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|INST_done 4 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|current_state_state_4 4 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|current_state_state_3 4 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|current_state_state_2 4 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0|current_state_state_0 4 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|crc16_0 100 0 0 0 85 0 0 0 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1|busy_reg_0 5 1 0 1 1 1 1 1 0 0 0 0 0
U_Open_bus_TP3_WB_ASP_1 78 0 0 0 92 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_Shifter|U_Shift_Barrel 40 0 0 0 32 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_Shifter 43 1 3 1 33 1 1 1 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_OCDS|U_JtagDebugUnit|TSK3000_DebugSignalController 9 0 0 0 6 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_OCDS|U_JtagDebugUnit|TSK3000_DebugPort|tsk3000_ControlRegister 12 0 0 0 6 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_OCDS|U_JtagDebugUnit|TSK3000_DebugPort|tsk3000_DebugDataRegister 40 0 0 0 34 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_OCDS|U_JtagDebugUnit|TSK3000_DebugPort|tsk3000_SubstituteRegister 41 0 0 0 34 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_OCDS|U_JtagDebugUnit|TSK3000_DebugPort|tsk3000_TapController 8 0 0 0 14 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_OCDS|U_JtagDebugUnit|TSK3000_DebugPort 72 0 0 0 76 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_OCDS|U_JtagDebugUnit 73 0 0 0 75 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_OCDS 72 2 0 2 71 2 2 2 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MDU|U_MultDiv|RegA_Abs_0_muladd_0_31_28__Z|auto_generated|ded_mult1|right_mult|pre_result 22 0 0 0 22 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MDU|U_MultDiv|RegA_Abs_0_muladd_0_31_28__Z|auto_generated|ded_mult1|right_mult 34 0 9 0 22 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MDU|U_MultDiv|RegA_Abs_0_muladd_0_31_28__Z|auto_generated|ded_mult1|left_mult|pre_result 18 0 0 0 18 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MDU|U_MultDiv|RegA_Abs_0_muladd_0_31_28__Z|auto_generated|ded_mult1|left_mult 30 0 9 0 18 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MDU|U_MultDiv|RegA_Abs_0_muladd_0_31_28__Z|auto_generated|ded_mult1 48 9 0 9 36 9 9 9 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MDU|U_MultDiv|RegA_Abs_0_muladd_0_31_28__Z|auto_generated 41 0 3 0 36 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MDU|U_MultDiv 79 0 0 0 43 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MDU 71 0 0 0 33 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MCU|U_InputSynchronizer 34 0 0 0 39 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MCU|U_MCU|ProgramCounter 139 0 0 0 33 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MCU|U_MCU|U_DataHazardResolverA 185 0 0 0 109 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MCU|U_MCU|U_Execute|U_ALU 76 0 0 0 47 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MCU|U_MCU|U_Execute|U_Bus_MuxB 50 0 0 0 32 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MCU|U_MCU|U_Execute|U_CalculateEffectiveAddress 48 0 0 0 32 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MCU|U_MCU|U_Execute|U_Execute_Mux 116 0 0 0 16 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MCU|U_MCU|U_Execute|U_ExecuteBusy 3 0 0 0 1 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MCU|U_MCU|U_Execute|U_MDU_EnableControl 3 0 0 0 1 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MCU|U_MCU|U_Execute|U_ProgramCounterControl|U_BranchComparator 74 0 0 0 6 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MCU|U_MCU|U_Execute|U_ProgramCounterControl|U_BranchTarget_Relative 46 0 0 0 30 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MCU|U_MCU|U_Execute|U_ProgramCounterControl|U_MakeReturnPC 33 0 0 0 30 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MCU|U_MCU|U_Execute|U_ProgramCounterControl 184 0 0 0 96 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MCU|U_MCU|U_Execute|U_ShiftAmountMux 11 0 0 0 5 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MCU|U_MCU|U_Execute|U_Shifter_EnableControl 3 0 0 0 1 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MCU|U_MCU|U_Execute|U_WriteSteering 4 0 0 0 2 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MCU|U_MCU|U_Execute 257 0 0 0 191 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MCU|U_MCU|U_InterruptController 92 0 0 0 117 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MCU|U_MCU|U_MemoryManager 232 0 0 0 136 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MCU|U_MCU|U_PipeLineController 27 0 0 0 23 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MCU|U_MCU|U_PipeStage_Decode 30 0 0 0 91 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MCU|U_MCU|U_ReadSteering|U_ReadSteering_Mux 58 0 0 0 28 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MCU|U_MCU|U_ReadSteering 58 0 0 0 28 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MCU|U_MCU|U_RegisterFile 277 0 0 0 200 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MCU|U_MCU|U_Registers_GP|ram|auto_generated 45 0 0 0 32 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MCU|U_MCU|U_Registers_GP|ram_1|auto_generated 45 0 0 0 32 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MCU|U_MCU|U_Registers_GP 49 0 0 0 106 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MCU|U_MCU|U_Registers_SP 222 0 0 0 86 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MCU|U_MCU|U_Regs_EX_MEM 323 0 0 0 154 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MCU|U_MCU|U_Regs_ID_EX 226 0 0 0 159 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MCU|U_MCU|U_Regs_IF_ID 48 0 0 0 34 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MCU|U_MCU|U_Regs_MEM_WB 55 0 0 0 49 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MCU|U_MCU 339 0 0 0 309 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_MCU 333 65 0 65 377 65 65 65 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_BootMemory|AND2_componentB4 2 0 0 0 1 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_BootMemory|AND2_componentB3 2 0 0 0 1 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_BootMemory|AND2_componentB2 2 0 0 0 1 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_BootMemory|AND2_componentB1 2 0 0 0 1 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_BootMemory|AND2_componentA4 2 0 0 0 1 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_BootMemory|AND2_componentA3 2 0 0 0 1 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_BootMemory|AND2_componentA2 2 0 0 0 1 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_BootMemory|AND2_componentA1 2 0 0 0 1 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4_component|altsyncram_component|auto_generated 48 0 0 0 16 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u4_component 48 0 0 0 16 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3_component|altsyncram_component|auto_generated 48 0 0 0 16 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u3_component 48 0 0 0 16 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2_component|altsyncram_component|auto_generated 48 0 0 0 16 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u2_component 48 0 0 0 16 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1_component|altsyncram_component|auto_generated 48 0 0 0 16 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_BootMemory|Memory_TSK3000A_1_u1_component 48 0 0 0 16 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TSK3000A_1_SubPart_BootMemory 104 38 0 38 65 38 38 38 0 0 0 0 0
U_Open_bus_TP3_TERM|U_terminal|RegisterAcknowledge 8 0 0 0 3 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TERM|U_terminal|RegisterConfiguration 9 0 0 0 2 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TERM|U_terminal|RegisterStatus 10 0 0 0 1 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TERM|U_terminal|RegisterWriteFromInstrument 8 0 0 0 9 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TERM|U_terminal|RegisterReadFromInstrument 14 0 0 0 1 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TERM|U_terminal|control_register 8 0 0 0 7 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TERM|U_terminal|TAP1|id_reg_unit 4 0 0 0 1 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TERM|U_terminal|TAP1 5 0 0 0 9 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TERM|U_terminal 21 0 0 0 13 0 0 0 0 0 0 0 0
U_Open_bus_TP3_TERM 21 1 0 1 10 1 1 1 0 0 0 0 0
U_Open_bus_TP3_GPIO|INST_pao_7 4 2 0 2 1 2 2 2 0 0 0 0 0
U_Open_bus_TP3_GPIO|INST_pao_6 4 2 0 2 1 2 2 2 0 0 0 0 0
U_Open_bus_TP3_GPIO|INST_pao_5 4 2 0 2 1 2 2 2 0 0 0 0 0
U_Open_bus_TP3_GPIO|INST_pao_4 4 2 0 2 1 2 2 2 0 0 0 0 0
U_Open_bus_TP3_GPIO|INST_pao_3 4 2 0 2 1 2 2 2 0 0 0 0 0
U_Open_bus_TP3_GPIO|INST_pao_2 4 2 0 2 1 2 2 2 0 0 0 0 0
U_Open_bus_TP3_GPIO|INST_pao_1 4 2 0 2 1 2 2 2 0 0 0 0 0
U_Open_bus_TP3_GPIO|INST_pao_0 4 2 0 2 1 2 2 2 0 0 0 0 0
U_Open_bus_TP3_GPIO 21 0 0 0 17 0 0 0 0 0 0 0 0