NiosII_mini

2011.03.20.11:51:21 Datasheet
Overview
  clk  NiosII_mini
   sorties
 out_port  
 in_port  
 rxd  
 txd  
Processor
   cpu_0 Nios II 10.1
All Components
   onchip_memory2_0 altera_avalon_onchip_memory2 10.1
   cpu_0 altera_nios2 10.1
   sorties altera_avalon_pio 10.1
   entrees altera_avalon_pio 10.1
   timer_0 altera_avalon_timer 10.1
   uart_0 altera_avalon_uart 10.1
   sysid altera_avalon_sysid 10.1
Memory Map
cpu_0
 instruction_master  data_master
  onchip_memory2_0
s1  0x00008000 0x00008000
  cpu_0
jtag_debug_module  0x00010800 0x00010800
  sorties
s1  0x00011040
  entrees
s1  0x00011050
  timer_0
s1  0x00011000
  uart_0
s1  0x00011020
  sysid
control_slave  0x00011060

clk

clock_source v10.1


Parameters

clockFrequency 50000000
clockFrequencyKnown true
inputClockFrequency 0
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

onchip_memory2_0

altera_avalon_onchip_memory2 v10.1
clk clk   onchip_memory2_0
  clk1
cpu_0 instruction_master  
  s1
data_master  
  s1


Parameters

allowInSystemMemoryContentEditor false
blockType AUTO
dataWidth 32
deviceFamily Cyclone II
dualPort false
initMemContent true
initializationFileName onchip_memory2_0
instanceID NONE
memorySize 32768
readDuringWriteMode DONT_CARE
simAllowMRAMContentsFile false
slave1Latency 1
slave2Latency 1
useNonDefaultInitFile false
useShallowMemBlocks false
writable true
generateLegacySim false
  

Software Assignments

ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
INIT_CONTENTS_FILE "onchip_memory2_0"
NON_DEFAULT_INIT_FILE_ENABLED 0
GUI_RAM_BLOCK_TYPE "Automatic"
WRITABLE 1
DUAL_PORT 0
SIZE_VALUE 32768u
SIZE_MULTIPLE 1
CONTENTS_INFO ""
RAM_BLOCK_TYPE "Auto"
INIT_MEM_CONTENT 1
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
INSTANCE_ID "NONE"
READ_DURING_WRITE_MODE "DONT_CARE"

cpu_0

altera_nios2 v10.1
clk clk   cpu_0
  clk
instruction_master   onchip_memory2_0
  s1
data_master  
  s1
data_master   sorties
  s1
data_master   entrees
  s1
data_master   timer_0
  s1
d_irq  
  irq
data_master   uart_0
  s1
d_irq  
  irq
data_master   sysid
  control_slave


Parameters

userDefinedSettings
tightlyCoupledInstructionMaster3MapParam
tightlyCoupledInstructionMaster3AddrWidth 1
tightlyCoupledInstructionMaster2MapParam
tightlyCoupledInstructionMaster2AddrWidth 1
tightlyCoupledInstructionMaster1MapParam
tightlyCoupledInstructionMaster1AddrWidth 1
tightlyCoupledInstructionMaster0MapParam
tightlyCoupledInstructionMaster0AddrWidth 1
tightlyCoupledDataMaster3MapParam
tightlyCoupledDataMaster3AddrWidth 1
tightlyCoupledDataMaster2MapParam
tightlyCoupledDataMaster2AddrWidth 1
tightlyCoupledDataMaster1MapParam
tightlyCoupledDataMaster1AddrWidth 1
tightlyCoupledDataMaster0MapParam
tightlyCoupledDataMaster0AddrWidth 1
setting_showUnpublishedSettings false
setting_showInternalSettings false
setting_shadowRegisterSets 0
setting_preciseSlaveAccessErrorException false
setting_preciseIllegalMemAccessException false
setting_preciseDivisionErrorException false
setting_performanceCounter false
setting_perfCounterWidth _32
setting_interruptControllerType Internal
setting_illegalMemAccessDetection false
setting_illegalInstructionsTrap false
setting_fullWaveformSignals false
setting_extraExceptionInfo false
setting_exportPCB false
setting_debugSimGen false
setting_clearXBitsLDNonBypass true
setting_branchPredictionType Automatic
setting_bit31BypassDCache true
setting_bigEndian false
setting_bhtPtrSz _8
setting_bhtIndexPcOnly false
setting_avalonDebugPortPresent false
setting_alwaysEncrypt true
setting_allowFullAddressRange false
setting_activateTrace true
setting_activateTestEndChecker false
setting_activateMonitors true
setting_activateModelChecker false
setting_HDLSimCachesCleared true
setting_HBreakTest false
resetSlave onchip_memory2_0.s1
resetOffset 0
muldiv_multiplierType EmbeddedMulFast
muldiv_divider false
mpu_useLimit false
mpu_numOfInstRegion 8
mpu_numOfDataRegion 8
mpu_minInstRegionSize _12
mpu_minDataRegionSize _12
mpu_enabled false
mmu_uitlbNumEntries _4
mmu_udtlbNumEntries _6
mmu_tlbPtrSz _7
mmu_tlbNumWays _16
mmu_processIDNumBits _8
mmu_enabled false
mmu_autoAssignTlbPtrSz true
mmu_TLBMissExcSlave
mmu_TLBMissExcOffset 0
manuallyAssignCpuID false
internalIrqMaskSystemInfo 3
instSlaveMapParam <address-map><slave name='onchip_memory2_0.s1' start='0x8000' end='0x10000' /><slave name='cpu_0.jtag_debug_module' start='0x10800' end='0x11000' /></address-map>
instAddrWidth 17
impl Tiny
icache_size _4096
icache_ramBlockType Automatic
icache_numTCIM _0
icache_burstType None
exceptionSlave onchip_memory2_0.s1
exceptionOffset 32
deviceFeaturesSystemInfo M512_MEMORY 0 M4K_MEMORY 1 M9K_MEMORY 0 M20K_MEMORY 0 M144K_MEMORY 0 MRAM_MEMORY 0 MLAB_MEMORY 0 ESB 0 EPCS 1 DSP 0 EMUL 1 HARDCOPY 0 LVDS_IO 0 ADDRESS_STALL 1 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 DSP_SHIFTER_BLOCK 0
deviceFamilyName Cyclone II
debug_triggerArming true
debug_level Level1
debug_jtagInstanceID 0
debug_embeddedPLL true
debug_debugReqSignals false
debug_assignJtagInstanceID false
debug_OCIOnchipTrace _128
dcache_size _2048
dcache_ramBlockType Automatic
dcache_omitDataMaster false
dcache_numTCDM _0
dcache_lineSize _32
dcache_bursts false
dataSlaveMapParam <address-map><slave name='onchip_memory2_0.s1' start='0x8000' end='0x10000' /><slave name='cpu_0.jtag_debug_module' start='0x10800' end='0x11000' /><slave name='timer_0.s1' start='0x11000' end='0x11020' /><slave name='uart_0.s1' start='0x11020' end='0x11040' /><slave name='sorties.s1' start='0x11040' end='0x11050' /><slave name='entrees.s1' start='0x11050' end='0x11060' /><slave name='sysid.control_slave' start='0x11060' end='0x11068' /></address-map>
dataAddrWidth 17
customInstSlavesSystemInfo <info/>
cpuReset false
cpuID 0
clockFrequency 50000000
breakSlave cpu_0.jtag_debug_module
breakOffset 32
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

CPU_IMPLEMENTATION "tiny"
BIG_ENDIAN 0
CPU_FREQ 50000000u
ICACHE_LINE_SIZE 0
ICACHE_LINE_SIZE_LOG2 0
ICACHE_SIZE 0
DCACHE_LINE_SIZE 0
DCACHE_LINE_SIZE_LOG2 0
DCACHE_SIZE 0
FLUSHDA_SUPPORTED
HAS_JMPI_INSTRUCTION
EXCEPTION_ADDR 0x8020
RESET_ADDR 0x8000
BREAK_ADDR 0x10820
HAS_DEBUG_STUB
HAS_DEBUG_CORE 1
CPU_ID_SIZE 1
CPU_ID_VALUE 0x0
HARDWARE_MULTIPLY_PRESENT 0
HARDWARE_MULX_PRESENT 0
HARDWARE_DIVIDE_PRESENT 0
INST_ADDR_WIDTH 17
DATA_ADDR_WIDTH 17

sorties

altera_avalon_pio v10.1
clk clk   sorties
  clk
cpu_0 data_master  
  s1


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 50000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 8
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 8
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 50000000u

entrees

altera_avalon_pio v10.1
clk clk   entrees
  clk
cpu_0 data_master  
  s1


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 50000000
direction Input
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 8
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 0
HAS_IN 1
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 8
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 50000000u

timer_0

altera_avalon_timer v10.1
clk clk   timer_0
  clk
cpu_0 data_master  
  s1
d_irq  
  irq


Parameters

alwaysRun false
counterSize 32
fixedPeriod false
period 1
periodUnits MSEC
resetOutput false
snapshot true
systemFrequency 50000000
timeoutPulseOutput false
timerPreset CUSTOM
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
FIXED_PERIOD 0
SNAPSHOT 1
PERIOD 1
PERIOD_UNITS "ms"
RESET_OUTPUT 0
TIMEOUT_PULSE_OUTPUT 0
FREQ 50000000u
LOAD_VALUE 49999ULL
COUNTER_SIZE 32
MULT 0.0010
TICKS_PER_SEC 1000u

uart_0

altera_avalon_uart v10.1
clk clk   uart_0
  clk
cpu_0 data_master  
  s1
d_irq  
  irq


Parameters

baud 9600
baudError 0.01
clockRate 50000000
dataBits 8
fixedBaud true
parity NONE
simCharStream
simInteractiveInputEnable false
simInteractiveOutputEnable false
simTrueBaud false
stopBits 1
syncRegDepth 2
useCtsRts false
useEopRegister false
useRelativePathForSimFile false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BAUD 9600
DATA_BITS 8
FIXED_BAUD 1
PARITY 'N'
STOP_BITS 1
SYNC_REG_DEPTH 2
USE_CTS_RTS 0
USE_EOP_REGISTER 0
SIM_TRUE_BAUD 0
SIM_CHAR_STREAM ""
FREQ 50000000u

sysid

altera_avalon_sysid v10.1
clk clk   sysid
  clk
cpu_0 data_master  
  control_slave


Parameters

id 0
timestamp 1300618274
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ID 0u
TIMESTAMP 1300618274u
generation took 0,00 seconds rendering took 0,13 seconds